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International Journal of VLSI Design & Communication Systems

ISSN Print: 0976-1527

ISSN Online:

Website: http://airccse.org/journal/vlsi/vlsics.html

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Performance Evaluation of Throughput Maximization in MC-CDMA for 4G Standard

Hema Kale,C.G. Dethe,M.M. Mushrif

Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology

Joyashree Bag,Rajanna K M,Subir Kumar Sarkar

Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data

Sunita M.S,Kanchana Bhaaskaran V.S

Synthesis Optimization for Finite State Machine Design in FPGAs

R.Uma,P.Dhavachelvan

A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology

Tarun Kr. Gupta,Kavita Khare

Design of Reversible Multipliers for Linear Filtering Applications in DSP

Rakshith Saligram,Rakshith T.R

Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates

H R Bhagyalakshmi,M K Venkatesha

Reduction of Bus Transition for Compressed Code Systems

S. R. Malathi,R. Ramya Asmi

Realization of Transmitter and Receiver Architecture for Downlink Channels in 3-GPP LTE

S. Syed Ameer Abbas,J. Rahumath Nisha,M. Beril Sahaya Mary,S. J. Thiruvengadam

A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

Hanie Ghaedrahmat,Khosrow Hajsadeghi

Generic System Verilog Universal Verification Methodology Based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPS/SOCS

Abhishek Jain,Giuseppe Bonanno,Hima Gupta,Ajay Goyal

An Efficient CNTFET Based 7-Input Minority Gate

Samira Shirinabadi Farahani,Ronak Zarhoun,Mohammad Hossein Moaiyeri,Keivan Navi

Dual Field Dual Core Secure Cryptoprocessor on FPGA Platform

C. Veeraraghavan,K. Rajendran

Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data

Vaishali Dhare,Usha Mehta

A Multi-Objective Perspective for Operator Scheduling Using Finegrained DVS Architectures

Rajdeep Mukherjee,Priyankar Ghosh,Pallab Dasgupta,Ajit Pal

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Anil Yadav,Gayatri Mehta,Alex K. Jones,Justin Stander

Ternary Tree Asynchronous Interconnect Network for GALS' SOC

Vivek E. Khetade,S.S. Limaye

Faster Interleaved Modular Multiplier Based on Sign Detection

Mohamed A. Nassar,Layla A. A. El-Sayed

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell

Viplav A. Soliv,Ajay A. Gurjar

A 3-14 GHZ Low Noise Amplifier for Ultra Wide Band Applications

Vaithianathan Venkatesan,Aishwarya Prabakaran,Anupreethi Balaji Ranganathan,Divya Santhanam

Performance Evaluation of CDMA Router for Network-On-Chip

Anant W. Hinganikar,Mahendra A. Gaikwad,Rajendra M. Patrikar

FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme

Durga Sowjanya,K N H Srinivas,P Venkata Ganapathi

Leakage Power Reduction and Analysis of CMOS Sequential Circuits

M. Janaki Rani,S. Malarkann

Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog

Addanki Purna Ramesh,A.V. N. Tilak,A.M.Prasad

A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation

Vasantha Kumar B.V.P,N. S. Murthy Sharma,K. Lal Kishore,Jibanjeet Mishra

Multi User Detector in CDMA Using Elliptic Curve Cryptography

M. Ranga Rao,B. Prabhakara Rao

Low Power Folded Cascode OTA

Swati Kundra,Priyanka Soni,Anshul Kundra

Modeling of Built-In Potential Variations of Cylindrical Surrounding Gate (CSG) MOSFETs

Santosh Kumar Gupta,S.Baishya

Design of Low Power Sigma Delta ADC

Mohammed Arifuddin Sohel,K. Chenna Kesava Reddy,Syed Abdul Sattar

VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

Rita M. Shende,Pritesh R. Gumble

Design and ASIC Implemenatation of DUC/DDC for Communication Systems

Naagesh S. Bhat

Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

Neenu Joseph,P Nirmal Kumar

Universal Rotate Invert Bus Encoding for Low Power VLSI

Shankaranarayana Bhat M,D. Yogitha Jahnavi

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

P.Rajeswari,A.R.Ashwatha,R.Ramesh

A New Full Adder Cell for Molecular Electronics

Mehdi Ghasemi,Mohammad Hossein Moaiyeri,Keivan Navi

Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit

Deeprose Subedi,Eugene John

CNFET Based Basic Gates and a Novel FullAdder Cell

Fazel Sharifi,Amir Momeni,keivan Navi

Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System

Chaitali Biswas Dutta,Partha Garai,Amitabha Sinha

Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application

Sonal Aggarwal,Rajbir Singh

Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

M.S.Suma,K.S.Gurumurthy

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

R.H.Talwekar,S.S Limaye

System on Programable Chip for Performance Estimation of Loom Machine

Gurpreet Singh,Ajay Kumar Roy,Surekha K S,Surekha K S

Logic Optimization Using Technology Independent MUX Based Adders in FPGA

R.Uma,P.Dhavachelvan

Area, Delay and Power Comparison of Adder Topologies

R.Uma,Vidya Vijayan,M. Mohanapriya,Sharon Paul

Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design

Kiran Agarwal Gupta,Dinesh K Anvekar,Venkateswarlu V

Fault Secure Encoder and Decoder with Clock Gating

N.Kapileswar,P.Vijaya Santhi

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Manoj kumar,Kusum Lata

High Speed Continuous-Time Bandpass Σ ADC for Mixed Signal VLSI Chips

P.A.HarshaVardhini,M.Madhavi Latha

Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits

Rajani H.P,Srimannarayan Kulkarni

An Efficient Approach for Four-Layer Channel Routing in VLSI Design

Ajoy Kumar Khan,Bhaskar Das,Tapas Kumar Bayen

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