Ternary Tree Asynchronous Interconnect Network for GALS' SOC

Interconnect fabric requires easy integration of computational block operating with unrelated clocks.Thispaper presents asynchronous interconnect with ternary tree asynchronous network for GloballyAsynchronous Locally Synchronous (GALS) system-on-chip (SOC). Here architecture is proposed forinterconnection with ternary tree asynchronous network where ratio of number NOC design unit andnumber of router is 4:1,6:2, 8:3,10:4 etc .It is scalable for any number of NOC design unit. It offersaneasy integration of different clock domain with lowcommunication overhead .NOC design unit for GALS‘SOC is formulated by wrapping synchronous module with input port along with input port controller,output port along with output port controller and local clock generator. It creates the interface betweensynchronous to asynchronous and asynchronous to synchronous. For this purpose four port asynchronousrouters is designed with routing element and outputarbitration and buffering with micro-pipeline. Thisinterconnect fabric minimizes silicon area, minimize Latency and maximize throughput. Here functionalmodel is made for TTAN and application MPEG4 is mapped on the Network .Desired traffic pattern isgenerated and performance of the network is evaluated. Significant improvement in the networkperformance parameter has been observed.