Synthesis Optimization for Finite State Machine Design in FPGAs

Synthesis optimization plays a vital role in modern FPGAs in order to achieve high performance, in termsof resource utilization and reducing time consuming test process. Cell-based design techniques, such asstandard-cells and FPGAs, together with versatile hardware synthesis are rudiments for a highproductivity in ASIC design. As the capacity of FPGAs increases, synthesis tools and efficient synthesismethods for targeted device become more significant to efficiently exploit the resources and logic capacity.The synthesis tool provides the selection of different constraint to optimize the circuit. This paper presentsthe design and synthesis optimization constraints in FPGA for Finite state machine. The primary goal ofthis sequential logic design is to optimize the speed and area by choosing the proper options available inthe synthesis tool. More over the work focuses the design of FSM with more processes operates at a fasterrate and the number of slices utilized in an FPGA is also reduced when compare to single process. Themodule functionality are described using Verilog HDL and performance issues like slice utilized,simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technologyusing SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.