International Journal of Reconfigurable Computing - oalib

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International Journal of Reconfigurable Computing

ISSN Print: 1687-7195

ISSN Online:

主页: http://www.hindawi.com/journals/ijrc/

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Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application

Wim Vanderbauwhede,S. R. Chalamalasetti,M. Margala

Evaluation of Runtime Task Mapping Using the rSesame Framework

Kamana Sigdel,Carlo Galuzzi,Koen Bertels,Mark Thompson,Andy D. Pimentel

Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels

Christoph Roth,Joachim Meyer,Michael Rückauer,Oliver Sander,Jürgen Becker

Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

Ali Akbar Zarezadeh,Christophe Bobda

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

Sascha Mühlbach,Andreas Koch

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography

Laurent Sauvage,Sylvain Guilley,Florent Flament,Jean-Luc Danger,Yves Mathieu

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Diana G？hringer,Lukas Meder,Stephan Werner,Oliver Oey,Jürgen Becker,Michael Hübner

A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

Lyndon Judge,Suvarna Mane,Patrick Schaumont

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

Gustavo Sanchez,Felipe Sampaio,Marcelo Porto,Sergio Bampi,Luciano Agostini

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

Tom Davidson,Fatma Abouelella,Karel Bruneel,Dirk Stroobandt

Exploring Many-Core Design Templates for FPGAs and ASICs

Ilia Lebedev,Christopher Fletcher,Shaoyi Cheng,James Martin,Austin Doupnik,Daniel Burke,Mingjie Lin,John Wawrzynek

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

Kaveh Aasaraai,Andreas Moshovos

A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

Lu Wan,Chen Dong,Deming Chen

Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response

Florent Bernard,Viktor Fischer,Crina Costea,Robert Fouquet

High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP

Khaled Benkrid,Ali Akoglu,Cheng Ling,Yang Song,Ying Liu,Xiang Tian

Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs

Rafael A. Arce-Nazario,José Ortiz-Ubarri

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

Angelo Kuti Lusala,Jean-Didier Legat

Modeling and Implementation of a Power Estimation Methodology for SystemC

Matthias Kuehnle,Andre Wagner,Alisson V. Brito,Juergen Becker

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme

Élvio Carlos Dutra e Silva Júnior,Leandro Soares Indrusiak,Weiler Alves Finamore,Manfred Glesner

Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)

Claudia Feregrino,Miguel Arias,Kris Gaj,Viktor K. Prasanna

HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs

Andrew G. Schmidt,Neil Steiner,Matthew French,Ron Sass

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures

Zoltán Endre Rákossy,Zheng Wang,Anupam Chattopadhyay

Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

Michael Schaeferling,Ulrich Hornung,Gundolf Kiefer

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

E. Romero-Aguirre,R. Parra-Michel,Roberto Carrasco-Alvarez,A. G. Orozco-Lugo

Open SystemC Simulator with Support for Power Gating Design

George Sobral Silveira,Alisson V. Brito,Helder F. de A. Oliveira,Elmar U. K. Melcher

Open SystemC Simulator with Support for Power Gating Design

George Sobral Silveira,Alisson V. Brito,Helder F. de A. Oliveira,Elmar U. K. Melcher

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

E. Romero-Aguirre,R. Parra-Michel,Roberto Carrasco-Alvarez,A. G. Orozco-Lugo

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures

Zoltán Endre Rákossy,Zheng Wang,Anupam Chattopadhyay

Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

Michael Schaeferling,Ulrich Hornung,Gundolf Kiefer

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme

élvio Carlos Dutra e Silva Júnior,Leandro Soares Indrusiak,Weiler Alves Finamore,Manfred Glesner

HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs

Andrew G. Schmidt,Neil Steiner,Matthew French,Ron Sass

Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)

Claudia Feregrino,Miguel Arias,Kris Gaj,Viktor K. Prasanna,Marco D. Santambrogio,Ron Sass

High-Performance Reconfigurable Computing

Khaled Benkrid,Esam El-Araby,Miaoqing Huang,Kentaro Sano,Thomas Steinke

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

John C. Hoffman,Marios S. Pattichis

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

Dominique Blouin,Daniel Chillet,Eric Senn,Sébastien Bilavarn,Robin Bonamy,Christian Samoyeau

Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates

Monica Magalh？es Pereira,Luigi Carro

FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition

Richard Veitch,Louis-Marie Aubert,Roger Woods,Scott Fischaber

Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems

Benjamin Glas,Oliver Sander,Vitali Stuckert,Klaus D. Müller-Glaser,Jürgen Becker

A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

Onur Derin,Erkan Diken,Leandro Fiorin

Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

Guilherme Perin,Daniel Gomes Mesquita,Jo？o Baptista Martins

Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems

Diana G？hringer,Jonathan Obie,André L. S. Braga,Michael Hübner,Carlos H. Llanos,Jürgen Becker

Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT

Matthias Birk,Clemens Hagner,Matthias Balzer,Nicole V. Ruiter,Michael Hübner,Jürgen Becker

FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

Tobias Schumacher,Tim Sü？,Christian Plessl,Marco Platzner

Operating System for Runtime Reconfigurable Multiprocessor Systems

Diana G？hringer,Michael Hübner,Etienne Nguepi Zeutebouo,Jürgen Becker

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment

Mateus B. Rutzig,Antonio C. S. Beck,Felipe Madruga,Marco A. Alves,Henrique C. Freitas,Nicolas Maillard,Philippe O. A. Navaux,Luigi Carro

On Self-Timed Circuits in Real-Time Systems

Markus Ferringer

A Streaming High-Throughput Linear Sorter System with Contention Buffering

Jorge Ortiz,David Andrews

The Potential for a GPU-Like Overlay Architecture for FPGAs

Jeffrey Kingyens,J. Gregory Steffan

Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs

Christian Schuck,Bastian Haetzer,Jürgen Becker

A Genetic Programming Approach to Reconfigure a Morphological Image Processing Architecture

Emerson Carlos Pedrino,José Hiroki Saito,Valentin Obac Roda

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