Due to the fast changing wireless communication standards coupled with strict performance constraints, the demand for flexible yet high-performance architectures is increasing. To tackle the flexibility requirement, software-defined radio (SDR) is emerging as an obvious solution, where the underlying hardware implementation is tuned via software layers to the varied standards depending on power-performance and quality requirements leading to adaptable, cognitive radio. In this paper, we conduct a case study for representatives of two complexity classes of WCDMA channel estimation algorithms and explore the effect of flexibility on energy efficiency using different implementation options. Furthermore, we propose new design guidelines for both highly specialized architectures and highly flexible architectures using high-level synthesis, to enable the required performance and flexibility to support multiple applications. Our experiments with various design points show that the resulting architectures meet the performance constraints of WCDMA and a wide range of options are offered for tuning such architectures depending on power/performance/area constraints of SDR. 1. Introduction In a scenario of fast changing standards and process technologies, mobile devices increasingly rely on the software-defined radio (SDR) and cognitive radio [1, 2] concepts to achieve adaptability, flexibility, and spectral and energy efficiency. SDR implementation presents an interesting challenge for the architecture designers, namely, to develop an underlying hardware platform for SDR with fine balance of performance and flexibility. This demanding problem led to major research activity in recent years [3–12]. One of the key ingredients in the SDR architecture design is to determine the algorithmic kernels across various standards. While the kernel can be implemented in the most efficient manner, it can be retargeted according to different standards by means of tunable parameters or weak programmability. To that effect, the final architecture can be an ASIC, a reconfigurable platform or an application-specific processor. The complete system is often built by combining such accelerators, targeted for different blocks of a wireless standard [7]. Often it is of great importance how such a system can adapt to changes in the algorithms or standards, saving some of the engineering and development costs when standards change. In this paper, we explore how flexibility can influence energy efficiency, area, and timing within the architectural design space of two wide-band code division
References
[1]
J. Mitola III, “Cognitive radio for flexible mobile multimedia communications,” in Proceedings of the IEEE International Workshop on Mobile Multimedia Communications (MoMuC '99), San Diego, Calif, USA, 1999.
[2]
J. Mitola, “Cognitive radio architecture evolution,” Proceedings of the IEEE, vol. 97, no. 4, pp. 626–641, 2009.
[3]
Y. Lin, H. Lee, M. Woh et al., “SODA: a low-power architecture for software radio,” in Proceedings of ACM SIGARCH Computer Architecture News, vol. 34, IEEE Computer Society, 2006.
[4]
K. Van Berkel, F. Heinle, P. P. E. Meuwissen, K. Moerman, and M. Weiss, “Vector processing as an enabler for software-defined radio in handheld devices,” Eurasip Journal on Applied Signal Processing, vol. 2005, no. 16, pp. 2613–2625, 2005.
[5]
M. Alles, T. Vogt, and N. Wehn, “FlexiChaP: a reconfigurable ASIP for convolutional, turbo, and LDPC code decoding,” in Proceedings of the 5th International Symposium on Turbo Codes and Related Topics (TURBOCODING '08), pp. 84–89, September 2008.
[6]
B. Bougard, B. De Sutter, D. Verkest, L. Van der Perre, and R. Lauwereins, “A coarse-grained array accelerator for software-defined radio baseband processing,” IEEE Micro, vol. 28, no. 4, pp. 41–50, 2008.
[7]
J. Glossner, D. Iancu, M. Moudgill et al., “The sandbridge SB3011 platform,” Eurasip Journal on Embedded Systems, vol. 2007, Article ID 56467, 2007.
[8]
E. M. Witte, F. Borlenghi, G. Ascheid, R. Leupers, and H. Meyr, “A scalable VLSI architecture for soft-input soft-output single tree-search sphere decoding,” IEEE Transactions on Circuits and Systems II, vol. 57, no. 9, pp. 706–710, 2010.
[9]
T. Vogt and N. Wehn, “A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 10, pp. 1309–1320, 2008.
[10]
X. Chen, A. Minwegen, Y. Hassan et al., “FLEXDET: flexible, efficient multi-mode MIMO detection using reconfigurable ASIP,” in Proceedings of IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp. 69–76, IEEE, 2012.
[11]
G. K. Rauwerda, P. M. Heysters, and G. J. M. Smit, “Towards software defined radios using coarse-grained reconfigurable hardware,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 3–12, 2008.
[12]
V. Derudder, B. Bougard, A. Couvreur et al., “A 200？Mbps + 2.14？nJ/b digital baseband multi processor system-on-chip for SDRs,” in Proceedings of the Symposium on VLSI Circuits, pp. 292–293, June 2009.
[13]
H. Holma and A. Toskala, WCDMA for UMTS, vol. 4, Wiley Online Library, 2000.
GAUT High Level Synthesis, http://www-labsticc.univ-ubs.fr/www-gaut/.
[16]
Bluespec, http://www.bluespec.com/.
[17]
Tensilica, http://www.tensilica.com/.
[18]
Synopsys Designware ARC, http://www.arc.com/.
[19]
A. Fauth, J. Van Praet, and M. Freericks, “Describing instruction set processors using nML,” in Proceedings of the European Conference on Design and Test, IEEE Computer Society, 1995.
[20]
A. Chattopadhyay, H. Meyr, and R. Leupers, LISA: A Uniform ADL for Embedded Processor Modelling, Implementation and Software Toolsuite Generation, Morgan Kaufmann, 2008.
G. Yue, X. Zhou, and X. Wang, “Performance comparisons of channel estimation techniques in multipath fading CDMA,” IEEE Transactions on Wireless Communications, vol. 3, no. 3, pp. 716–724, 2004.
[23]
S. Abeta, M. Sawahashi, and F. Adachi, “Performance comparison between time-multiplexed pilot channel and parallel pilot channel for coherent Rake combining in DS-CDMA mobile radio,” IEICE Transactions on Communications, vol. E81-B, no. 7, pp. 1417–1425, 1998.
[24]
U. J. Kapasi, W. J. Dally, S. Rixner, J. D. Owens, and B. Khailany, “The imagine stream processor,” in Proceedings of the International Conference on Computer Design: VLSI in Computer & Processors (ICCD '92), pp. 282–288, September 2002.
[25]
S. Rajagopal, S. Rixner, and J. R. Cavallaro, “A programmable baseband processor design for software defined radios,” in Proceedings of the 45th Midwest Symposium on Circuits and Systems, vol. 3, pp. III413–III416, August 2002.
[26]
B. Mei, A. Lambrechts, D. Verkest, J. Y. Mignolet, and R. Lauwereins, “Architecture exploration for a reconfigurable architecture template,” IEEE Design and Test of Computers, vol. 22, no. 2, pp. 90–101, 2005.
[27]
C. Ebeling, D. Cronquist, and P. Franklin, “Rapid reconfigurable pipelined datapath,” in Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, pp. 126–135, 1996.
[28]
H. Singh, M. H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications,” IEEE Transactions on Computers, vol. 49, no. 5, pp. 465–481, 2000.
[29]
E. Waingold, M. Taylor, D. Srikrishna et al., “Computer baring it all to software: raw machines,” Computer, vol. 30, no. 9, pp. 86–93, 1997.
[30]
K. Karuri, A. Chattopadhyay, X. Chen et al., “A design flow for architecture exploration and implementation of partially reconfigurable processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 10, pp. 1281–1294, 2008.
[31]
A. DeHon, “Density advantage of configurable computing,” Computer, vol. 33, no. 4, pp. 41–49, 2000.
[32]
H. Fujisawa, M. Saito, S. Nishijima et al., “Flexible signal processing platform chip for software defined radio with 103 GOPS dynamic reconfigurable logic cores,” in Proceedings of IEEE Asian Solid-State Circuits Conference (ASSCC '06), pp. 67–70, November 2006.
[33]
O. Gustafsson, K. Amiri, D. Andersson et al., “Architectures for cognitive radio testbeds and demonstrators—an overview,” in Proceedings of the 5th International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CROWNCom '10), pp. 1–6, June 2010.
[34]
P. D. Sutton, J. Lotze, H. Lahlou et al., “Iris: an architecture for cognitive radio networking testbeds,” IEEE Communications Magazine, vol. 48, no. 9, pp. 114–122, 2010.
[35]
S. Rajagopal, S. Bhashyam, J. R. Cavallaro, and B. Aazhang, “Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers,” IEEE Transactions on Wireless Communications, vol. 1, no. 3, pp. 468–479, 2002.
[36]
S. Rajagopal, B. Jones, J. Cavallaro, et al., “Task partitioning wireless base-station receiver algorithms on multiple dsps and fpgas,” in Proceedings of the International Conference on Signal Processing, Applications, and Technology (ICSPAT '00), Dallas, Tex, USA, 2000.
[37]
S. Rajagopal, S. Bhashyam, J. R. Cavallaro, and B. Aazhang, “Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 31, no. 2, pp. 143–156, 2002.
[38]
A. Kuehlmann and R. A. Bergamaschi, “High-level state machine specification and synthesis,” in Proceedings of the International Conference on Computer Design: VLSI in Computer & Processors (ICCD '92), pp. 536–539, 1992.
[39]
J. David and E. Bergeron, “An intermediate level HDL for system level design,” in Proceedings of the Forum on specification & Design Languages (FDL '04), pp. 526–536, 2004.
[40]
Z. Wang, Z. Rakosi, X. Wang, and A. Chattopadhyay, “ASIC synthesis using architecture description language,” in Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT '12), 2012.
