Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms. 1. Introduction Past decade has witnessed a change in the design of powerful processors. It has been realized that running processors at higher and higher frequencies is not sustainable due to unproportional increases in power consumption. This led to the design of multicore chips, usually consisting of multiprocessor symmetric Systems on Chip (MPSoCs), with limited numbers of CPU-L1 cache nodes interconnected by simple bus connections and capable in turn of becoming nodes in larger multiprocessors. However, as the number of components in these systems increases, communication becomes a bottleneck and it hinders the predictability of the metrics of the final system. Networks on Chip (NoCs) [1] emerged as a new communication paradigm to address scalability issues of MPSoCs. Still, achieving goals such as easy parallel programming, good load balancing and ultimate performances, dependability and low-power consumption pose new challenges for such architectures. Technology scaling decreases the yield in manufacturing and thermal effects cause defects at run time. Thus fault tolerance becomes a major concern not only for economical reasons but also for the end user. In addressing these issues, we adopted a component-based approach based on Kahn Process Networks (KPNs) for specifying the applications [2]. KPN is a stream-oriented model of computation based on the idea of organizing an application into streams and computational blocks; streams represent the flow of data, while computational blocks represent operations on a stream of data. KPN
References
[1]
G. De Micheli and L. Benini, Networks on Chips: Technology and Tools, Morgan Kaufmann, Burlington, Mass, USA, 2006.
[2]
G. Kahn, “The semantics of a simple language for parallel programming,” in Proceedings of the IFIP Congress (Information Processing '74), J. L. Rosenfeld, Ed., pp. 471–475, North-Holland Puplishing Company, New York, NY, USA, 1974.
[3]
O. Derin and A. Ferrante, “Simulation of a self-adaptive run-time environment with hardware and software components,” in Proceedings of the ESEC/FSE Workshop on Software Integration and Evolution at Runtime (SINTER '09), pp. 37–40, ACM, New York, NY, USA, August 2009.
[4]
O. Derin and A. Ferrante, “Enabling self-adaptivity in componentbased streaming applications,” SIGBED Review, vol. 6, no. 3, special issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES '09), 2009.
[5]
O. Derin, A. Ferrante, and A. V. Taddeo, “Coordinated management of hardware and software self-adaptivity,” Journal of Systems Architecture, vol. 55, no. 3, pp. 170–179, 2009.
E. Carara, A. Mello, and F. Moraes, “Communication models in networks-on-chip,” in Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), pp. 57–60, IEEE Computer Society, Washington, DC, USA, 2007.
[8]
T. Stefanov, C. Zissulescu, A. Turjan, B. Kienhuis, and E. Deprettere, “System design using Kahn process networks: the compaan/laura approach,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 1, p. 10340, Paris, France, February 2004.
[9]
A. Nieuwland, J. Kang, O. P. Gangwal, et al., “C-heap: a heterogeneous multi-processor architecture template and scalable and flexible protocol for the design of embedded signal processing systems,” Design Automation for Embedded Systems, vol. 7, pp. 233–270, 2002.
[10]
S. Kwon, Y. Kim, W. C. Jeun, S. Ha, and Y. Paek, “A retargetable parallel-programming framework for MPSoC,” ACM Transactions on Design Automation of Electronic Systems, vol. 13, no. 3, pp. 1–39, 2008.
[11]
I. Bacivarov, W. Haid, K. Huang, and L. Thiele, “Methods and tools for mapping process networks onto multi-processor systems-on-chip,” in Handbook of Signal Processing Systems, S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, and J. Takala, Eds., pp. 1007–1040, Springer, 2010.
[12]
W. Haid, L. Schor, K. Huang, I. Bacivarov, and L. Thiele, “Efficient execution of kahn process networks on multi-processor systems using protothreads and windowed fifos,” in Proceedings of the IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia '09), pp. 35–44, IEEE, Grenoble, France, 2009.
[13]
“Multicore associations communication api.,” http://www.multicore-association.org.
[14]
“A high performance message passing library,” http://www.open-mpi.org/.
[15]
G. M. Almeida, G. Sassatelli, P Benoit, et al., “An adaptive message passing MPSoC framework,” International Journal of Reconfigurable Computing, vol. 2009, p. 20, 2009.
[16]
A. B. Nejad, K. Goossens, J. Walters, and B. Kienhuis, “Mapping kpn models of streaming applications on a network-on-chip platform,” in Proceedings of the Workshop on Signal Processing, Integrated Systems and Circuits(ProRISC '2009), November 2009.
[17]
E. Beigne, F. Clermidy, P. Vivet, A. Clouard, and M. Renaudin, “An asynchronous noc architecture providing low latency service and its multi-level design framework,” in Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp. 54–63, IEEE Computer Society, Washington, DC, USA, 2005.
[18]
I. Koren and C. M. Krishna, Fault Tolerant Systems, Morgan Kaufmann, San Francisco, Calif, USA, 2007.
[19]
A. Avizienis, “The n-version approach to fault-tolerant software,” IEEE Transactions on Software Engineering, vol. 11, no. 12, pp. 1491–1501, 1985.
[20]
M. R. Lyu, Handbook of Software Reliability Engineering, McGraw-Hill, Hightstown, NJ, USA, 1996.
[21]
C. Fuhrman, S. Chutani, and H. Nussbaumer, “A fault-tolerant implementation using multiple-task triple modular redundancy,” in Proceedings of the IEEE International Workshop on Factory Communication Systems (WFCS '95), pp. 75–80, October 1995.
[22]
M. Rebaudengo, M. S. Reorda, and M. Violante, “A new approach to software-implemented fault tolerance,” Journal of Electronic Testing, vol. 20, no. 4, pp. 433–437, 2004.
[23]
E. L. Rhod, C. A. Lisb?a, L. Carro, M. Sonza Reorda, and M. Violante, “Hardware and software transparency in the protection of programs against SEUs and SETs,” Journal of Electronic Testing, vol. 24, no. 1–3, pp. 45–56, 2008.
[24]
J. Ceponis, E. Kazanavicius, and A. Mikuckas, “Fault tolerant process networks,” Information Technology and Control, vol. 35, no. 35, pp. 124–130, 2006.
[25]
J. ?eponis, E. Kazanavi?ius, and L. ?eponiene, “Handling multiple failures in process networks,” Information Technology and Control, vol. 37, no. 1, pp. 19–25, 2008.
[26]
T. M. Parks, Bounded scheduling of process networks, Ph.D. thesis, University of California, Berkeley, Calif, USA, December 1995.
[27]
S. Murali and G. De Micheli, “Bandwidth-constrained mapping of cores onto NoC architectures,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 2, pp. 896–901, February 2004.
[28]
L. Thiele, I. Bacivarov, W. Haid, and K. Huang, “Mapping applications to tiled multiprocessor embedded systems,” in Proceedings of the 7th International Conference on Application of Con-currency to System Design (ACSD '07), pp. 29–40, July 2007.
[29]
T. T. Ye, L. Benini, and G. De Micheli, “Packetized on-chip interconnect communication analysis for mpsoc,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '03), vol. 1, p. 10344, IEEE Computer Society, Washington, DC, USA, 2003.
[30]
“Sesc simulator,” http://sesc.sourceforge.net.
[31]
K. Reick, P. N. Sanda, S. Swaney et al., “Fault-tolerant design of the IBM Power6 microprocessor,” IEEE Micro, vol. 28, no. 2, pp. 30–38, 2008.
[32]
D. K. Pradhan and N. H. Vaidya, “Roll-forward checkpointing scheme: a novel fault-tolerant architecture,” IEEE Transactions on Computers, vol. 43, no. 10, pp. 1163–1174, 1994.
[33]
A. Antola, F. Ferrandi, V. Piuri, and M. Sami, “Semiconcurrent error detection in data paths,” IEEE Transactions on Computers, vol. 50, no. 5, pp. 449–465, 2001.