A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units

In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction.