%0 Journal Article
%T A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units
%A Ashwini Suresh Deshmukh
%J International Journal of Reconfigurable and Embedded Systems (IJRES)
%D 2012
%I Institute of Advanced Engineering and Science (IAES)
%R 10.11591/ijres.v1i1.378
%X In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction.
%U http://iaesjournal.com/online/index.php/IJRES/article/view/378