Designs including tens of millions of standard cells in one chip are commonly used in current IC projects, so finding optimal location on a chip surface for each logic cell is a very important step in IC design. Apart from finding room for logic cell placement with minimum chip area, length of connecting wires is also playing big role and needs to be taken under control. In this paper, research and implementation of standard cell placement-optimizations’ quadratic algorithm is described. Main research is on runtime and wire length. For 5K standard cells, algorithm implementation takes 83 second.
Cite this paper
Abazyan, S. , Mamikonyan, N. and Janpoladov, V. (2020). Standard Cell Placement Optimization Using Quadratic Placement Algorithm. Open Access Library Journal, 7, e6218. doi: http://dx.doi.org/10.4236/oalib.1106218.
Chan, T., Cong, J., Kong, T. and Shinnerl, J. (2000) Multilevel Optimization for Large-Scale Circuit Placement. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 5-9 November 2000, 171-176.
Chan, T., Cong, J., Kong, T., Shinnerl, J. and Sze, K. (2003) An Enhanced Multilevel Algorithm for Circuit Placement. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 9-13 November 2003, 299-305.
https://doi.org/10.1109/ICCAD.2003.159704
Huang, D.J.-H. and Kahng, A.B. (1997) Partitioning Based Standard Cell Global Placement with an Exact Objective. ACM/IEEE International Symposium on Physical Design, Napa Valley, CA, April 1997, 18-25.
https://doi.org/10.1145/267665.267674
Agnihotri, A.R. and Madden, P.H. (2007) Fast Analytic Placement Using Minimum Cost Flow. Asia and South Pacific Design Automation Conference, Yokohama, 23-26 January 2007, 128-134. https://doi.org/10.1109/ASPDAC.2007.357974
Chen, J. and Zhu, W. (2012) An Analytical Placer for VLSI Standard Cell Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31, 1208-1221. https://doi.org/10.1109/TCAD.2012.2190289
Chu, C. (2008) “Chapter 11: Placement” in Electronic Design Automation: Synthesis Verification and Testing. Elsevier/Morgan Kaufmann, San Francisco, CA.