This work summarizes the structure and
operating features of a high-performance 3-stage dual-delay-path (DDP)
voltage-controlled ring oscillator (VCRO) with self-biased delay cells for
Phase-Locked Loop (PLL) structurebased clock generation and digital system
driving. For a voltage supply VDD = 1.8 V, the resulting set of performance
parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz =
-107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high
performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC
L180), the proposed VCRO was designed at Cadence environment and optimized at
MunEDA WiCkeD tool.
References
[1]
Jovanovic, G., Stojcev, M. and Stamenkovic, Z. (2010) A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability. Scientific Publications of the State University of Novi Pazar, 2, 1-9.
[2]
Park, C.-H., Kim, O. and Kim, B. (2001) A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching. IEEE Journal of Solid-State Circuits, 36, 777-783. https://doi.org/10.1109/4.918915
[3]
Sun, L.Z. and Kwasniewski, T.A. (2001) A 1.25-GHz 0.35 μm Monolithic CMOS PLL Based on a Multiphase Ring Oscillator. IEEE Journal of Solid-State Circuits, 36, 910-916. https://doi.org/10.1109/4.924853
[4]
Savoj, B. and Razavi, B. (2001) A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector. IEEE Journal of Solid-State Circuits, 36, 761-768. https://doi.org/10.1109/4.918913
[5]
Yang, C.-K.K., Farjad-Rad, R. and Horowitz, M.A. (1998) A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling. IEEE Journal of Solid-State Circuits, 33, 713-722. https://doi.org/10.1109/4.668986
[6]
Alioto, M. and Palumbo G. (2001) Oscillation Frequency in CML and ESCL Ring Oscillators. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 48, 210-214. https://doi.org/10.1109/81.904885
[7]
Razavi, B. (1997) Oscillation Frequency in CML and ESCL Ring Oscillators. IEEE Journal of Solid-State Circuits, 32, 730-735. https://doi.org/10.1109/4.568843
[8]
Tomar, A. and Pokharel, R. K. and Nizhnik, O. and Kanaya, H. and Yoshida, K. (2007) Design of 1.1 GHz Highly Linear Digitally-Controlled Ring Oscillator with Wide Tuning Range. IEEE International Workshop on Radio-Frequency Integration Technology, Singapore, 9-11 December 2007, 82-85. https://doi.org/10.1109/RFIT.2007.4443926
[9]
Betancourt-Zamora R.J. and Lee, T.H. (1998) CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry. International Symposium on Low Power Electronics and Design, Monterey, 10-12 August 1998, 91-94. https://doi.org/10.1145/280756.280798
[10]
Jalil J., Reaz, M.B.I., Rahman, L.F., Marufuzzaman, M. and Amin, M.S. (2012) A 2.45 GHz CMOS Voltage Controlled Oscillator for Active Transponder. International Conference on Advances in Circuits, Electronics and Micro-Electronics, 19-24 August 2012, Rome, 1-4.
[11]
Liu, H.Q., Siek, L., Goh, W.L. and Lim, W.M. (2008) A 7-GHz Multiloop Ring Oscillator in 0.18-μm CMOS Technology. Analog Integrated Circuits and Signal Processing, 56, 179-184. https://doi.org/10.1007/s10470-008-9163-z
[12]
Rezayee, A. and Martin, K. (2001) A Coupled Two-Stage Ring Oscillator. Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, 4, 878-881.
[13]
Tao, R. and Berroth, M. (2003) The Design of 5 GHz Voltage Controlled Ring Oscillator Using Source Capacitively Coupled Current Amplifier. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 9-10 June 2003, 623-626.
[14]
Pinto A.M., Iano, Y., Manera, L. and Souza, R.R.N. (2015) An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads. International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, 9, 408-412.
[15]
de Matos Pinto, A., Souza, R.R.N., Iano Y. and Manera L.T. (2015) WiCkeD Tool-Based Design Method for Divide-by-2 Circuits with Multiple Loads. 2015 European Microelectronics Packaging Conference, Friedrichshafen, 14-16 September 2015, 1-5.
[16]
de Matos Pinto Jr., A., Souza, R.R.N., Manera, L.T., Solano, J.E.V., Chagas, C.M. and Finco, S. (2018) Design of the Voltage-Controlled Ring Oscillator Using Optimization Tools (MunEDA WiCkeD). In: Iano, Y., Arthur, R., Saotome, O., Vieira Estrela, V. and Loschi, H., Eds., Proceedings of the 3rd Brazilian Technology Symposium, Springer, Berlin, 179-192. https://doi.org/10.1007/978-3-319-93112-8_19
[17]
Pelgrom, M.J.M., Duinmaijer, A.C.J. and Welbers, A.P.G. (1989) Matching Properties of MOS Transistors. IEEE Journal of Solid-State Circuits, 24, 1433-1439. https://doi.org/10.1109/JSSC.1989.572629
[18]
Jalil, J., Reaz, M.B.I., Bhuiyan, M.A.S., Rahman, L.F. and Chang, T.G. (2014) Designing a Ring VCO for RFID Transponders in 0.18 μm CMOS Process. The Scientific World Journal, 2014, Article ID: 580385. https://doi.org/10.1155/2014/580385
[19]
Tong, T., Wenhua, Z., Hvolgaard, J.M. and Larsen, T. (2007) A 0.18 μm CMOS Low Power Ring VCO with 1 GHZ Tuning Range for 3-5 GHZ FM-UWB Applications. 10th IEEE Singapore International Conference on Communication Systems, Singapore, 30 October-1 November 2006, 1-5. https://doi.org/10.1109/ICCS.2006.301371
[20]
Zhang, C., Li, Z., Fang, J., Zhao, J., Guo, Y. and Chen, J. (2014) A Novel High-Speed CMOS Fully-Differentical Ring VCO. 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, Guilin, 28-31 October 2014, 1-3. https://doi.org/10.1109/ICSICT.2014.7021580
[21]
Ramiah, H., Keat, C.W. and Kanesan, J. (2014) Design of Low-Phase Noise, Low-Power Ring Oscillator for OC-48 Application. IETE Journal of Research, 58, 425-428. https://doi.org/10.4103/0377-2063.104161
[22]
Pokharel, R.K., Nizhnik, O., Tomar, A., Lingala, S., Kanaya, H. and Yoshida, K. (2009) Wide Tuning Range CMOS Quadrature Ring Oscillator of Best Figure-of-Merit. European Microwave Integrated Circuits Conference, Rome, 28-29 September 2009, 172-175.
