%0 Journal Article
%T Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation
%A Agord de Matos Pinto Jr
%A Raphael Ronald Noal Souza
%A Mateus Biancarde Castro
%A Eduardo Rodrigues de Lima
%A Leandro Tiago Man¨ºra
%J Circuits and Systems
%P 19-28
%@ 2153-1293
%D 2023
%I Scientific Research Publishing
%R 10.4236/cs.2023.146003
%X This work summarizes the structure and
operating features of a high-performance 3-stage dual-delay-path (DDP)
voltage-controlled ring oscillator (VCRO) with self-biased delay cells for
Phase-Locked Loop (PLL) structurebased clock generation and digital system
driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance
parameters include power consumption P<sub><span style=\"text-wrap:wrap;\"><sub></sub></span>DC</sub><span style=\"text-wrap:wrap;\"></span> = 4.68 mW and phase noise <em>PN</em>@<em>1MHz</em> =
-107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub><span style=\"text-wrap:wrap;\"></span> and PN, a system level high
performance is obtained considering a reference figure-of-merit ( <em>FoM</em> = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC
L180), the proposed VCRO was designed at Cadence environment and optimized at
MunEDA WiCkeD tool.
%K Phase Locked Loop (PLL)
%K Voltage-Controlled Ring Oscillators (VCRO)
%K Dual-Delay-Path DDP
%K Delay Cells
%U http://www.scirp.org/journal/PaperInformation.aspx?PaperID=128466