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- 2018
The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling TransistorDOI: 10.1186/s11671-018-2483-8 Keywords: Tunneling FET (TFET), DRAM, Spacer engineering, Retention time Abstract: a Schematic of dual-gate TFET (DGTFET) DRAM cell. b Comparison between simulated transfer characteristic with experimental results for SOI TFET [25
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