%0 Journal Article
%T The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor
%A Hongxia Liu
%A Qianqiong Wang
%A Shulong Wang
%A Shupeng Chen
%A Wei Li
%J Archive of "Nanoscale Research Letters".
%D 2018
%R 10.1186/s11671-018-2483-8
%X a Schematic of dual-gate TFET (DGTFET) DRAM cell. b Comparison between simulated transfer characteristic with experimental results for SOI TFET [25
%K Tunneling FET (TFET)
%K DRAM
%K Spacer engineering
%K Retention time
%U https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5838025/