Design and Implementation of Memory Access Fast Switching Structure in Cluster-Based Reconfigurable Array Processor
Design and Implementation of Memory Access Fast Switching Structure in Cluster-Based Reconfigurable Array Processor

Memory access fast switching structures in cluster are studied, and three kinds of fast switching structures (FS, LR2SS, and LAPS) are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT, FFT, SAD, IME, FME, and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures, our proposed structures have lower data access delay and lower area.
Memory access fast switching structures in cluster are studied, and three kinds of fast switching structures (FS, LR2SS, and LAPS) are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT, FFT, SAD, IME, FME, and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures, our proposed structures have lower data access delay and lower area.