A novel double-node-upset-resilient radiation-hardened latch

To effectively tolerate a double-node upset, a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology. Using three interlocked single-node-upset-resilient cells, which are identically mainly constructed from three mutually feeding back 2-input C-elements, the latch achieves double-node-upset-resilience. Using smaller transistor sizes, clock-gating technology, and high-speed transmission-path, the cost of the latch is effectively reduced. Simulation results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches, the proposed latch reduces the transmission delay by 72.54%, the power dissipation by 33.97%, and the delay-power-area product by 78.57%, while the average cost of the silicon area is only increased by 16.45%.