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OALib Journal期刊
ISSN: 2333-9721
费用：99美元
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ldpc码硬件仿真平台的fpga实现
DOI: 10.13232/j.cnki.jnju.2014.03.011
Keywords: ldpc码,误码平底,解码器,架构,fpga
Abstract:
低密度奇偶校验（ldpc）码的误码平底现象一直是研究的热点。软件仿真评估ldpc码的纠错能力大约能达到200kbps左右的吞吐率，需要10才能仿真到10-7水平。基于硬件加速技术的性能仿真能够大大加快仿真速度，可以比软件仿真快10000倍以上，使误码平底的实验研究成为可能。本文采用fpga实现了ldpc码的硬件仿真平台，整个系统的吞吐率达120mbps，使仿真速度大大提升。给出了硬件仿真系统的整体架构以及编码器，解码器，高斯白噪声产生器等主要模块的结构和资源消耗。
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