Chang H,Sapatnekar S S.Statistical Timing analysis under spatial correlations [J].IEEE Transactions on Computer Aided Design,2005,24(9):1467-1482.
[2]
Le J,Li X,Pileggi L T.STAC:Statistical Timing analysis with correlation [A].ACM/EDAC/IEEE Design Automation Conference [C].Massachusetts:MIT Press,2005.343-348.
[3]
Shinkai K,Hashimoto M,et al.A gate delay model focusing on current fluctuation over wide-range of process and environmental variability [A].Proc ICCAD [C].Massachusetts:MIT Press,2006.47-53.
[4]
Gray P R,Meyer R G.Analysis and Design of Analog Integrated Circuits[M].New York:Wiley,1984.
[5]
Predictive Technology Model [OL].http://ptm.asu.edu,2013.
[6]
Papoulis A.Probability,Random Variables and Stochastic Process[M].New York:McGraw Hill,1991.
[7]
Mehrotra V,Sam S,et al.A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance [A].Design Automation Conference [C].Massachusetts:MIT Press,2000.172-175.
[8]
Li X,Janet M,et al.Stochastic Analysis of interconnect delay in presence of process variations [J].Journal of Semiconductors,2008,29(2):304-309.
[9]
Nassif S R.Modeling and Forecasting of manufacturing variations [A].IEEE Custom Integrated Circuit Conference [C].Massachusetts:MIT Press,2001.223-226.
Chen P,Kirkpatrick D A,Keutzer K.Static Crosstalk-Noise Analysis[M].New York:Kluwer Academic Publisher,2004.
[15]
Liu P,Pileggi L T,Strojwas A J.Model order reduction or RC interconnect including variational analysis [A].Design Automation Conferenc [C].Massachusetts:MIT Press,1999.201-206.
[16]
Junmou Z,Eby G F.Decoupling Technique and crosstalk analysis for coupled RLC interconnects [A].Proceeding ISCAS [C].Massachusetts:MIT Press,2004.521-524.
[17]
Ghanta P,Vrudhula S,et al.Stochastic power grid analysis considering process variations [A].IEEE Design,Automation,and Test [C].Massachusetts:MIT Press,2005.21-25.