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电子学报  2015 

基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法

DOI: 10.3969/j.issn.0372-2112.2015.03.006, PP. 454-459

Keywords: 三维嵌入式芯核,测试外壳扫描链,跨度,虚拟层

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Abstract:

为减少三维芯核绑定前和绑定后的测试时间,降低测试成本,提出了基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法.所提方法首先通过最大化每条测试外壳扫描链的跨度,使得绑定前高层电路和低层电路的测试外壳扫描链数量尽可能相等.然后,在TSVs(ThroughSiliconVias)数量的约束下,逐层的将虚拟层中的扫描元素分配到测试外壳扫描链中,以平衡绑定前后各条测试外壳扫描链的长度.实验结果表明,所提方法有效地减少了三维芯核绑定前后测试的总时间和硬件开销.

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