Mahammad SN,Veezhinathan K.Constructing online testable circuits using reversible logic[J].IEEE Trans on Instrumentation and Measurement,2010,59 (1):101-109.
[2]
Kochete M A,Zoellin C G,Wunderlich H J.Efficient concurrent self-test with partially specified patterns[J].Journal of Electronic Testing Theory and Applications,2010,26(5):581-594.
[3]
Reviriego P,Maestro J A,Liu S F.Efficient soft error-tolerant adaptive equalizers[J].IEEE Transactions on Circuits Devices & Systems I-regular Papers,2010,57(8):2032-2040.
[4]
Shnidman R,Mangione-Smith H,Potkonjak M.On-line fault detection for bus-based field programmable gate arrays[J].IEEE Trans on Very Large Scale Integration(VLSI) System,1998,6(4):656-666.
[5]
Gupta K,Pradhan K.Utilization of on-line (concurrent) checkers during built-in self-test and vice versa[J].IEEE Transactions on Computers,1996,45(1):63-73.
[6]
Lalal P K,Burress A L.Self-checking logic design for FPGA implementation[J].IEEE Trans on Instrumentation and Measurement,2003,53(5):1391-1398.
[7]
A-Asaad H,Moore P.Non-concurrent on-line testing via scan chains [A].Proc of the IEEE Autotestcon Conference [C].Anaheim,CA:IEEE,2006.683-689
[8]
姚睿,王友仁,于盛林,陈则王.具有在线修复能力的强容错三模冗余系统设计及实验研究.电子学报,2010,38 (1):177-183. Yao R,Wang Y R,Yu S L,Chen Z W.Design and experiments of enhanced fault-tolerant triple-module redundancy systems capable of online self-repairing[J].Acta Electronica Sinica,2010,38(1):177-183.(in Chinese)
[9]
王友仁,张砦,袁鹏,孔德明.可重构硬件芯片级故障定位与自主修复方法[J].电子学报,2012,40(2):385-388. Wang Y R,Zhang Z,Yuan P,Kong D M.In-chip fault localization and self-repairing method for reconfigurable hardware[J].Acta Electronica Sinica,2012,40(2):385-388.(in Chinese)