USB2.0设备控制器IP核的Verilog HDL设计
, PP. 66-70
Keywords: USB,IP核,VerilogHDL
Abstract:
介绍了一种设计USB20设备控制器IP核的方法.着重分析了UTMI接口、协议层、存储器接口、仲裁器及控制和状态寄存器等几个结构模块及其设计.使用上述方法在XilinxISE软件平台上,实现了USB20设备控制器IP核的VerilogHDL语言代码及其验证
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