PATHIRANA V,NAPOLI E,UDREA F,et al.An analytical model for the lateral insulated gate bipolar transistor(LIGBT)on thin SOI[J].IEEE Transactions on Power Electronics,2006,21(6):1521-1528.
[2]
CHEN Wu-jun,ZHANG Bo,LI Zhao-ji.Realizing high breakdown voltage SJ-LDMOS on bulk silicon using a partial n-buried layer[J].Chinese Journal of Semiconductors,2007,28(3):355-360.
[3]
KIM H W,KIM S C,SEO K S,et al.Devicecharacteristics of the SOI LIGBT with dual-epi layers[C]∥International Power Electronics and Motion Control Conference,Xi'an,August14-16,2004:859-862.
[4]
KHANNA V K,KUMAR A,SOOD S C,et al.Investigation of degeneracy of current-voltage characteristics of asymmetrical IGBT with n-buffer layer concentration[J].Solid State Electronics,2001,45(10):1859-1865.
[5]
OH J K,KIM D Y,LEE B H.A dual-gate shorted-anode silicon-on-insulator lateral insulated gate bipolar transistor with floating ohmic contact for suppressing snapback and fast switching characteristics[J].Microelectronics Journal,1999,30(6):577-581.
[6]
BYEONA D S,CHUN J H,LEE B H,et al.The separated shorted-anode insulated gate bipolar transistor with the suppressed negative differential resistance regime[J].Microelectronics Journal,1999,30(6):571-575.
[7]
CAI Jun,SIN J K O.Latch-up characteristics of a lateral trench gate conductivity modulated power transistor[J].Journal of University of Science and Technology of China,1998,29(4):481-486.
[8]
CHEN Wan-jun,ZHANG Bo,LI Zhao-ji,et al.A novel high voltage LDMOS for HVIC with the multiple step shaped equipotential rings[J].Solid-state Electronics,2007,51(3):394-397.
[9]
ADAN A O,NAKA T,KAGISAWA A,et al.SOI as a mainstream IC technology[C]∥SOI Conference,Florida,October5-8,1998:9-12.
[10]
XIE Gang,ZHANG Bo.Self-clamping thyristor mode LIGBT based on SOI[C]∥EDSSC,Hongkong,December 8-10,2008:1-4.
[11]
CAI Jun,SIN J,MOK P,et al.A new lateral trench gate conductivity modulated power transistor[J].IEEE Transactions on Electron Devices,1999,46(8):1788-1793.
[12]
DISNEY D R,PEIN H B,PLUMMER J D.A trench gateLIGBT structure and two LMCT structures in SOI substrates[C]∥International Symposium on Power Semiconductor Devices and ICs,Switzerland,May31-June2,1994:405-410.
[13]
KANG Ey-goo,MOON Seung-hyun,SUNG Man-young.A new trench electrode IGBT for having superior electrical characteristics for power IC systems[J].Microelectronics Journal,2001,32(8):641-647.
[14]
HAN Seung-youp,NA Long-min,CHOI Yearn-lk,et al.An analytical model of the breakdown voltage and minimum epi layer length for RESURF pn diodes[J].Solid State Electronics,1995,39(8):1247-1248.
[15]
MEER H,MEYER K.Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide[J].Solid State Electronics,2001,45(4):593-598.
[16]
HENKEL I,FEILER W,KOSTKA A.A two dimensional analytical model for the current distribution in a lateral IGBT[J].Solid State Electronics,2001,45(10):1725-1732.
[17]
ZHANG Hai-peng,SUN Ling-ling,JIANG Li-fei,et al.Process simulation of trench gate and plate and trench drain SOI NLIGBT with TCAD tools[C]∥APCCAS,Macao,November30-December3,2008:1037-1040.
