Sklansky J. An evaluation of several two-summand binary adders[J].IRE Trans on Electron Computers, 1960(9):213-226.
[2]
Sklansky J. Conditional-sum addition logic[J]. IRE Trans on Electron Computers, 1960(9):226-231.
[3]
Ike T, Hanyu T, Kameyama M. Fully source-coupled logic based multiple-valued VLSI[C]//Proceedings of 32nd IEEE International Symposium on Multiple-Valued Logic. Boston, Massachusetts, USA: IEEE, 2002:270-275.
[4]
Natsui Masanori, Arimitsu Takashi, Hanyu Takahiro. Low-energy pipelined multiple-valued current-mode circuit with 8-level static current source control[C]//Proceedings of The International Symposium on Multiple-Valued Logic. Barcelona, Spain: IEEE, 2010:235-240.
[5]
Shirahama H, Mochizuki A. Design of a processing element based on quaternary differential logic for a multi-core SIMD processor[C]//Proceedings of 37th IEEE International Symposium on Multiple-Valued Logic. Oslo, Norway:ISMVL,2007:300-305.
[6]
Hanyu T, Mochizuki A, Kameyama M. Multiple-valued dynamic source-coupled logic[C]//Proceedings of 33rd IEEE International Symposium on Multiple-Valued Logic. Tokyo, Japan: IEEE Comput. Soc, 2003:207-212.
[7]
Rawat K, Darwish T,Bayoumi M. A low power and reduced area carry select adder[C]//Proceedings of 45th Midwest Symposium on Circuits and Systems. Tulsa, OK, USA: IEEE, 2002:467-470.
[8]
Wey Ichyn, Chow Hwangcherng. A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design[C]//Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. Fukuoka, Japan: IEEE, 2004:500-503.
