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基于多值逻辑的高性能片上总线设计

Keywords: 片上总线,多值逻辑,地址预置

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Abstract:

针对深亚微米条件下线延迟超越器件的延迟影响芯片性能的问题,提出一种新的片上总线模型和架构.采用多值逻辑传输模式实现片上模块间的通信;采用地址预置技术,提高基于四值逻辑的片上模块间的数据传输效率.ADMS仿真结果表明,相对于二值地址预置总线,在保持相同数据吞吐量时,可以使总线的数量明显减少;在保持相同总线数目时,数据吞吐量提高2倍.

References

[1]  Zhang Liang, John Wilson, Bashirulla R, et al. A 32 Gbit/s on-chip bus with driver pre-emphasis signaling //Proceedings of IEEE Custom Intergrated Circuits Conference (CICC). San Jose, CA: IEEE, 2006:265-268.
[2]  Atul Maheshwari, Wayne Burleson. Differential current-sensing for on-chip interconnects[J]. IEEE Transactions on Very Large Scale Intergation (VLSI) Systems, 2004,12(12):1321-1329.
[3]  Davis J, Venkatesan R, Kaloyeros A, et al.Interconnect limits on gigascale integration (GSI) in the 21st century[J]. Proceedings of IEEE, 2001,89(3):305-324.
[4]  Shirahama H, Mochizuki A. Design of a processing element based on quaternary differential logic for a multi-core SIMD processor //Proceedings of 37th IEEE International Symposium on Multiple-Valued Logic. Oslo: , 2007:43.
[5]  Hanyu T, Mochizuki A, Kameyama M. Multiple-valued dynamic source coupled logic //Proceedings of 33rd IEEE International Symposium on Multiple-Valued Logic. Tokyo, Japan: , 2003:207-212.
[6]  Mochizuki A, Takeuchi T, Hanyu T. Intra-chip address-presetting data-transfer scheme using four-valued encoding //Proceedings of 34th Int. Symp on Multiple-Valued Logic. Toronto, Canada: ISMVL, 2004:192-197.
[7]  Venkatraman V, Burleson W. An energy-efficient multi-bit quaternary current mode signaling for on-chip interconnects //Proceedings of IEEE Custom Intergrated Circuits Conference (CICC). San Jose, CA: IEEE, 2007:301-304.
[8]  Matsuura T, Shirahama H. Timing variation aware multiple-valued current-mode circuit for a low-power pipelined system //Proceedings of 39th International Symposium on Multiple-Valued Logic. Naha, Okinawa: , 2009:60-65.
[9]  Natsui Masanori, Arimitsu Takashi, Hanyu Takahiro. Low-energy pipelined multiple-valued current-mode circuit with 8-level static current-source control //Proceedings of the International Symposium on Multiple-Valued Logic. Barcelona, Spain: , 2010:235-240.
[10]  Zer E ?, Sendag R, Gregg D. Multiple-valued logic buses for reducing bus energy in low-power systems[J]. IEE Proc. of Comput Digit Tech, 2006,153(4):270-282.

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