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基于FPGA的准循环LDPC码低时延译码器设计

Keywords: 准循环LDPC码,低时延译码,FPGA实现,流水线

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Abstract:

针对准循环低密度奇偶校验码(LDPC码),提出一种基于FPGA的低延时译码器硬件实现结构.该译码器基于最小和译码算法,充分利用FPGA的RAM存储结构及流水线运算方式提高译码吞吐量,降低译码时延.该结构适用于大部分准循环LDPC码,且译码迭代一次只需约2倍缩放因子大小的时钟数量.与非流水线译码结构相比,在不增加资源占有率的情况下,译码时延降低到原来的1/7.

References

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