安彤, 秦飞, 武伟, 于大全, 万里兮, 王珺. TSV转接板上硅通孔的热应力分析[J]. 工程力学, 2013, 30(7): 262―269. An Tong, Qin Fei, Wu Wei, Yu Daquan, Wan Lixi, Wang Jun. Analysis of thermal stress in through silicon via of interposer [J]. Engineering Mechanics, 2013, 30(7): 262―269. (in Chinese)
[2]
Riebling J. Finite element modeling of ball grid array components [D]. Binghamton, New York: State University of New York at Binghamton, 1996.
[3]
Tsai T Y, Yeh C L, Lai Y S, et al. Transient sub-modeling analysis for board-level drop tests of electronic packages [J]. IEEE Transactions on Electronics Packaging Manufacturing, 2007, 30(1): 54―62.
[4]
Gu J, Lim C T, Tay A A O. Modeling of solder joint failure due to PCB Electronics Packaging bending during drop impact [C]. Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004: 678―683.
[5]
Zhang Z, Sitaraman S K, Wong C P. FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process [J]. IEEE Transactions on Electronics Packaging Manufacturing, 2004, 27(1): 86―93.
[6]
Pang J H L, Chong D Y R. Flip chip on board solder joint reliability analysis using 2-D and 3-D FEA models [J]. IEEE Transactions on Advanced Packaging, 2001, 24(4): 499―506.
[7]
Lee C C, Chang K C, Yang Y W. Lead-free solder joint reliability estimation of flip chip package using FEM-based sensitivity analysis [J]. Soldering & Surface Mount Technology, 2009, 21(1): 31―41.
[8]
Gu J, Lim C T, Tay A A O. Simulation of mechanical response of solder joints under drop impact using equivalent layer models [C]. Electronic Components and Technology Conference, 2005. Proceedings. 55th. IEEE, 2005: 491―498.
[9]
陈思, 秦飞, 夏国峰. TSV转接板组装工艺对微凸点可靠性的影响[J]. 工程力学, 2015, 32(6): 251―256. Chen Si, Qin Fei, Xia Guofeng. Effects of The TSV interposer assembly process on the reliably of microbumps [J]. Engineering Mechanics, 2015, 32(6): 251―256. (in Chinese)
[10]
Chang C L, Tsung F Y, Chih S W, et al. Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill [J]. Microelectronic Engineering, 2013, 107(7): 107―113.
[11]
An T, Qin F, Wu W, et al. An equivalent model of tsv silicon interposer [C]. Guilin, China: International Conference on Electronic Packaging Technology & High Density Packaging, 2012: 583―587.
[12]
沈观林, 胡更开. 复合材料力学[M]. 北京: 清华大学出版社, 2006: 267―299. Shen Guanlin, Hu Gengkai. Compound material mechanics [M]. Beijing: Tsinghua University Publishers, 2006: 267―299. (in Chinese)
[13]
Yang F, Meguid S A. Efficient multi-scale modeling technique for determining effective board drop reliability of PCB assembly [J]. Microelectronic Reliability, 2013, 53(7): 975―984.
[14]
秦飞, 王珺, 万里兮, 等. TSV结构热机械可靠性研究综述[J]. 半导体技术, 2012, 37(11): 825―831. Qin Fei, Wang Jun, Wan Lixi, et al. Review on the thermal mechanical reliability of TSV structure [J]. Semiconductor Technology, 2012, 37(11): 825―831. (in Chinese)
[15]
Anand L. Constitutive equations for hot-working of metals [J]. International Journal of Plasticity, 1985, 1(3): 213―231.
[16]
JESD22-A104C, Jedec Standard [S]. Arlington, VA, United states: Jedec Solid State Technology Association, 2005.
[17]
Darveaux R, Turlik I, Hwang L T, et al. Thermal stress analysis of a multichip package design [J]. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 1989, 12(4): 663―672.
