Harmanani H, Aoun H. An incremental approach for test scheduling and synthesis using genetic algorithms//Proceedings of the Second IEEE NEWCAS. Montreal: IEEE Press, 2004: 69-72.
[2]
Hariyama M, Aoyama T, Kameyama M. Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages[J]. IEEE Transactions on Computers, 2005, 54(6): 642-650.
[3]
孙强, 周涛, 马光胜. 一种基于遗传算法的高层次测试综合方法[J]. 计算机工程与应用, 2007, 43(30): 20-22. Sun Qiang, Zhou Tao, Ma Guangsheng. Genetic algorithm based high level test synthesis[J]. Chinese Journal of Computer Engineering and Applications, 2007, 43(30): 20-22.
[4]
Lee M T. High-level test synthesis of digital vlsi circuits[M]. Norwood: Artech House, 1997. 36-62.
[5]
Sun Qiang, Zhou Tao. A novel register allocation algorithm for testability[J]. Tsinghua Science and Technology, 2007, 12(S1): 57-60.
[6]
Safari S, Jahangir A H, Esmaeilzadeh H. A parameterized graph-based framework for high-level test synthesis[J]. Integration, the VLSI Journal, 2006, 39(4): 363-381.
[7]
Hermanani H, Saliba R, An evolutionary algorithm for the testable allocation problem in high-level synthesis[J]. J Circuits Syst Comput, 2005, 14(2): 347-366.
