Implementation of a Sec-ded Code with FPGA Xilinx Circuits to the Cache Level of a Memory Hierarchy

In this paper we will apply a SEC-DED code to the cache level of a memory hierarchy. From the category of SEC-DED (Single Error Correction Double Error Detection) codes we select the Hsiao code. The Hsiao code is an odd-weight-column SEC-DED code. For correction of single-bit error we use a syndrome decoder, a syndrome generator and the check bits generator circuit.