%0 Journal Article
%T Implementation of a Sec-ded Code with FPGA Xilinx Circuits to the Cache Level of a Memory Hierarchy
%A OVIDIU NOVAC
%A POSZET OTTO
%A VARI KAKAS STEFAN
%A MIRCEA VL£¿DU£¿IU
%J Journal of Computer Science and Control Systems
%D 2008
%I Editura Universit??ii din Oradea
%X In this paper we will apply a SEC-DED code to the cache level of a memory hierarchy. From the category of SEC-DED (Single Error Correction Double Error Detection) codes we select the Hsiao code. The Hsiao code is an odd-weight-column SEC-DED code. For correction of single-bit error we use a syndrome decoder, a syndrome generator and the check bits generator circuit.
%K SEC-DED code
%K Hsiao code
%U http://electroinf.uoradea.ro/reviste%20CSCS/documente/JCSCS_2008/JCSCS_2008_12_Novac_1.pdf