Design and Implementation of Area and Power Optimised Novel Scanflop

The power consumption of IC during test mode is higher than its normal mode. This brings the power asone of the major design constraints for today’s low power design technologies. In normal scan based testcircuits most of the power consumed due to the switching activity of scanflops during shift and capturecycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop forclock and it reduces the power consumption of the circuit and it also reduces area and test time too. Theproposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bitsof test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during itsdata mode. The design and functionality of the proposed scanflop is discussed and compared with thedifferent flipflops which shows that the proposed scan flop reduces the test time and clock switchingactivity by 50%, area by 30% and static power by 25%.