Design of optimized Interval Arithmetic Multiplier

Many DSP and Control applications that require the user to know how various numericalerrors(uncertainty) affect the result. This uncertainty is eliminated by replacing non-interval values withintervals. Since most DSPs operate in real time environments, fast processors are required to implementinterval arithmetic. The goal is to develop a platform in which Interval Arithmetic operations areperformed at the same computational speed as present day signal processors. So we have proposed thedesign and implementation of Interval Arithmetic multiplier, which operates with IEEE 754 numbers. Theproposed unit consists of a floating point CSD multiplier, Interval operation selector. This architectureimplements an algorithm which is faster than conventional algorithm of Interval multiplier . The costoverhead of the proposed unit is 30% with respect to a conventional floating point multiplier. Theperformance of proposed architecture is better than that of a conventional CSD floating-point multiplier,as it can perform both interval multiplication and floating-point multiplication as well as Intervalcomparisons