PIPELINED ARCHITECTURE OF 2D-DCT, QUANTIZATION AND ZIGZAG PROCESS FOR JPEG IMAGE COMPRESSION USING VHDL

This paper presents the architecture and VHDL design of a Two Dimensional Discrete Cosine Transform(2D-DCT) with Quantization and zigzag arrangement. This architecture is used as the core and path inJPEG image compression hardware. The 2D- DCT calculation is made using the 2D- DCT Separabilityproperty, such that the whole architecture is divided into two 1D-DCT calculations by using a transposebuffer. Architecture for Quantization and zigzag process is also described in this paper. The quantizationprocess is done using division operation. This design aimed to be implemented in Spartan-3E XC3S500FPGA. The 2D- DCT architecture uses 1891 Slices, 51I/O pins, and 8 multipliers of one Xilinx Spartan-3EXC3S500E FPGA reaches an operating frequency of 101.35 MHz One input block with 8 x 8 elements of 8bits each is processed in 6604 ns and pipeline latency is 140 clock cycles .