MODELLING AND SIMULATION OF 128-BIT CROSSBAR SWITCH FOR NETWORK -ONCHIP

This is widely accepted that Network-on-Chip represents a promising solution for forthcoming complexembedded systems. The current SoC Solutions are built from heterogeneous hardware and Softwarecomponents integrated around a complex communication infrastructure. The crossbar is a vital componentof in any NoC router. In this work, we have designed a crossbar interconnect for serial bit data transferand 128-parallel bit data transfer. We have shown comparision between power and delay for the serial bitand parallel bit data transfer through crossbar switch. The design is implemented in 0.180 micron TSMCtechnology.The bit rate achived in serial transfer is slow as compared with parallel data transfer. Thesimulation resuls show that the critical path delay is less for parallel bit data transfer but power dissipationis high.