Design and test challenges in Nano-scale analog and mixed CMOS technology

The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS)technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC) design andtesting have become a real challenge to ensure the functionality and quality of the product. The first part ofthe paper presents the CMOS technology scaling impact on design and reliability for consumer and criticalapplications. We then propose a discussion on the role and challenges of testing analog and mixed devicesin the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects ofbridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistivepath between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp) and a Built in Current Sensor (BICS) to validate the technique and correlate it with post layoutsimulation results.