Design and Implementation of Low Ripple Low Power Digital Phase-Locked Loop

We propose a phase-locked loop (PLL) architecture which reduces doublefrequency ripple without increasing the order of loop filter. Proposed architectureuses quadrature numerically–controlled oscillator (NCO) to provide two outputsignals with phase difference of p / 2 . One of them is subtracted from the inputsignal before multiplying with the other output of NCO. The system also providesstability in case the input signal has noise in amplitude or phase. The proposedstructure is implemented using field programmable gate array (FPGA) whichdissipates 15.44 mW and works at clock frequency of 155.8 MHz.