%0 Journal Article
%T Design and Implementation of Low Ripple Low Power Digital Phase-Locked Loop
%A M. Saber
%A Yutaka Jitsumatsu
%A Mohamed Tahit Khan
%J Signal Processing : An International Journal
%D 2011
%I Computer Science Journals
%X We propose a phase-locked loop (PLL) architecture which reduces doublefrequency ripple without increasing the order of loop filter. Proposed architectureuses quadrature numerically¨Ccontrolled oscillator (NCO) to provide two outputsignals with phase difference of p / 2 . One of them is subtracted from the inputsignal before multiplying with the other output of NCO. The system also providesstability in case the input signal has noise in amplitude or phase. The proposedstructure is implemented using field programmable gate array (FPGA) whichdissipates 15.44 mW and works at clock frequency of 155.8 MHz.
%K Digital Phase-Locked Loop (DPLL)
%K Field Programmable Gate Array (FPGA)
%K Numericallycontrolled Oscillator (NCO)
%K Read Only Memory (ROM)
%K Look-Up Table (LUT).
%U http://cscjournals.org/csc/manuscript/Journals/SPIJ/volume4/Issue6/SPIJ-99.pdf