A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator

This paper analyzes and designs a second order digital phase-locked loop (DPLL), and presentslow power architecture for DPLL. The proposed architecture reduces the high power consumptionof conventional DPLL, which results from using a read only memory (ROM) in implementation ofthe numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, inwhich no ROM is used. DPLL is designed and implemented using FPGA, consumes 237 mw,which means more than 25% saving in power consumption, and works at faster clock frequencycompared to traditional architecture.