%0 Journal Article %T A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator %A Mohamed Saber Saber Elsayes %A Yutaka Jitsumatsu %A Mohamed tahir Abasi Khan %J Signal Processing : An International Journal %D 2011 %I Computer Science Journals %X This paper analyzes and designs a second order digital phase-locked loop (DPLL), and presentslow power architecture for DPLL. The proposed architecture reduces the high power consumptionof conventional DPLL, which results from using a read only memory (ROM) in implementation ofthe numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, inwhich no ROM is used. DPLL is designed and implemented using FPGA, consumes 237 mw,which means more than 25% saving in power consumption, and works at faster clock frequencycompared to traditional architecture. %K Digital Phase locked loop (DPLL) %K Field Programmable Gate Array (FPGA) %K Software Defined Radio (SFDR) %K Read Only Memory (ROM) %K Spurious Free Dynamic Range (SFDR). %U http://cscjournals.org/csc/manuscript/Journals/SPIJ/volume5/Issue4/SPIJ-149.pdf