Design and Analysis of On-Chip Router for Network On Chip

Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip.For this efficient routers are needed to takes place communication between these devices. This paper gives thedesign of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.