%0 Journal Article
%T Design and Analysis of On-Chip Router for Network On Chip
%A Ms. A.S. Kale #1
%J International Journal of Computer Trends and Technology
%D 2011
%I Seventh Sense Research Group
%X Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip.For this efficient routers are needed to takes place communication between these devices. This paper gives thedesign of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.
%K Arbiter
%K Network on chip (NOC)
%K Router
%U http://www.ijcttjournal.org/volume-1/Issue-3/IJCTT-V1I3P112.pdf