Characterization of Defect Traps in SiO2 Thin Films

In order to understand the degradation of the electrical operations of metal-oxide-semiconductor (MOS) devices, this work is concerned by the defects generation processes in the non-stoichiometric SiOx, area and at the SiO2 interface. For this purpose, a new measurement technique to study slow-state traps and their relationship with fast-state traps is developed. This method considers capacitance-voltage measurements and temperature effects during the hysteresis cycle.