Ant colony optimization approach for test scheduling of system on chip

It is necessary to perform the test of system on chip, the test scheduling determines the test start and finishing time of every core in the system on chip such that the overall test time is minimized. A new test scheduling approach based on chaotic ant colony algorithm is presented in this paper. The optimization model of test scheduling was studied, the model uses the information such as the scale of test sets of both cores and user defined logic. An approach based on chaotic ant colony algorithm was proposed to solve the optimization model of test scheduling. The test of signal integrity faults such as crosstalk were also investigated when performing the test scheduling. Experimental results on many circuits show that the proposed approach can be used to solve test scheduling problems.