Timing Analysis and Design for DDR3 System
DDR3时序分析与设计

DDR3 memory has become mainstream application in current server and computer system.Though many techniques such as dual reference voltage,dynamic on-die termination(ODT),fly-by topology and write-leveling,have been adopt by DDR3 to improve signal integrity to a certain extent,it is difficult to design and realize high data rate.Combined with the design of a creative processor and correspondent server board,this paper introduced the basis theory of DDR3 source synchronous signal in brief at first,and analyzed the key factors affacting the DDR3 system timing quantative using simulation software in time domain,then calculated the timing margin for DDR3 write operation.Simulation result shows that the duty-cycle of signal become worse 3%~5% with the change of ODT value and the number of I/O simulatenous switching,and the timing skew due to crosstalk can reach 218ps.