Design and Verification of Clock Domain Crossing for SOC
面向soc芯片的跨时钟域设计和验证

With the increasing number of clock domains and CDC signals in today's high-performance,low-power SOC,the design and verification of CDC problem become more and more important. Traditional verification methods can notfind a comprehensive cross-clock domain design of functional errors in the RTL stage. In this paper, we dicussed 5 types of CDC synchronizer circuit templates of our chip, and proposed hiberarchy verification method: structural analysis, assertion-based verification, and formal verification. Taped sample chip tests show all CDC designs work right, and demonstrate that design and verification method arc effective and complete.