%0 Journal Article
%T Design and Verification of Clock Domain Crossing for SOC<br>面向soc芯片的跨时钟域设计和验证
%A LUO Li
%A HE Hong-jun
%A XU Wei-xi
%A DOU Qiang
%A <br>罗莉
%A 何鸿君
%A 徐炜遐
%A 窦强
%J 计算机科学
%D 2011
%I 
%X With the increasing number of clock domains and CDC signals in today's high-performance,low-power SOC,the design and verification of CDC problem become more and more important. Traditional verification methods can notfind a comprehensive cross-clock domain design of functional errors in the RTL stage. In this paper, we dicussed 5 types of CDC synchronizer circuit templates of our chip, and proposed hiberarchy verification method: structural analysis, assertion-based verification, and formal verification. Taped sample chip tests show all CDC designs work right, and demonstrate that design and verification method arc effective and complete.
%K Clock domain crossing design
%K Assertion-based verification
%K PSL(Property Specification Language)
%K Symbo-lic model checking
%K LTL logic<br>跨时钟域设计，基于断言的验证，PSI_属性说明语言，符号模型检查，LTL线性时序逻辑
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=64A12D73428C8B8DBFB978D04DFEB3C1&aid=A72829DDE955E0D294B486B9FD7867AA&yid=9377ED8094509821&vid=16D8618C6164A3ED&iid=9CF7A0430CBB2DFD&sid=69E4C201C13601F9&eid=C1B34927D429E92F&journal_id=1002-137X&journal_name=计算机科学&referenced_num=0&reference_num=0