RTL Low Power Technique for SoC Design Using Weighted Datapath
基于加权数据通路的RTL级低功耗SoC设计

Low-power is an important specification of SoC design and evaluation, a new low power design scheme was proposed by using weighted datapath. Firstly, the algorithm uses program slicing technictue to extract RTL data path.Secondly, the weights(frequcncy of use) of datapath arc obtained via Baycsian network training, and then the weighted datapath is generated. Finally, to reduce system power consumption effectively, the scheme controls the generation of clock gating logic, and it gives high priority for the datapath with low weight to insert or merge clock gating logic. Experimental results show that the proposed scheme has low computation cost, and it has 8. 38 %lower power consumption and 6. 8% lower hardware arear overhead when compared with existing low power SoC design scheme.