%0 Journal Article
%T RTL Low Power Technique for SoC Design Using Weighted Datapath<br>基于加权数据通路的RTL级低功耗SoC设计
%A YANG Heng-fu
%A TIAN Zu-wei
%A LI Yong-fan
%A <br>杨恒伏
%A 田祖伟
%A 李勇帆
%J 计算机科学
%D 2011
%I 
%X Low-power is an important specification of SoC design and evaluation, a new low power design scheme was proposed by using weighted datapath. Firstly, the algorithm uses program slicing technictue to extract RTL data path.Secondly, the weights(frequcncy of use) of datapath arc obtained via Baycsian network training, and then the weighted datapath is generated. Finally, to reduce system power consumption effectively, the scheme controls the generation of clock gating logic, and it gives high priority for the datapath with low weight to insert or merge clock gating logic. Experimental results show that the proposed scheme has low computation cost, and it has 8. 38 %lower power consumption and 6. 8% lower hardware arear overhead when compared with existing low power SoC design scheme.
%K System on chip
%K Low power design
%K Register transfer level
%K Weighted datapath<br>SoC，低功耗设计，寄存器传输级，加权数据通路
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=64A12D73428C8B8DBFB978D04DFEB3C1&aid=C93D86353453861A8D75362D02883937&yid=9377ED8094509821&vid=16D8618C6164A3ED&iid=0B39A22176CE99FB&sid=2AC7DCCBBC26ECF8&eid=AF507FDD66D991DA&journal_id=1002-137X&journal_name=计算机科学&referenced_num=0&reference_num=10