Easy Test Generation PLAs

Test Generation for large circuits may be extremely difficult.One of the approaches to alleviatingthis problem is to consider the difficulties during the design cycle.This paper proposes a design of EasyTest Generation Programmable Logic Arrays(ETG PLAs),for which test generation is basically notrequired,since a complete test set can be generated while the test is applied.This paper also presents aprocedure which makes a PLA an ETG PLA by following some design rules and providing reasonableextra hardware.