A maximum time difference pipelined arithmetic unit based on CMOS gate array
A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array

This paper describes a maximum time difference pipelined arithmetic chip, the 36-bit adder and subtractor based on 1.5 μm CMOS gate array. The chip can operate at 60MHz, and consumes less than 0.5 Watt. The results are also studied, and a more precise model of delay time difference is proposed. Project supported by National Natural Science Foundation of China under grant No.9689009.