%0 Journal Article
%T A maximum time difference pipelined arithmetic unit based on CMOS gate array<br>A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array
%A Zhimin Tang
%A Peisu Xia
%A <br>Tang Zhimin
%A Xia Peisu
%J 计算机科学技术学报
%D 1995
%I 
%X This paper describes a maximum time difference pipelined arithmetic chip, the 36-bit adder and subtractor based on 1.5 μm CMOS gate array. The chip can operate at 60MHz, and consumes less than 0.5 Watt. The results are also studied, and a more precise model of delay time difference is proposed. Project supported by National Natural Science Foundation of China under grant No.9689009.
%K Adder
%K CMOS
%K gate array maximum time difference
%K wave pipeline<br>加法器
%K CMOS
%K 门阵列
%K 最大时间差
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=6844B7FCB87C639DDBA461D38711F68B&yid=BBCD5003575B2B5F&vid=F3090AE9B60B7ED1&iid=0B39A22176CE99FB&sid=C3BF5C58156BEDF0&eid=89F76E117E9BDB76&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=0&reference_num=6