Byte access method for wide data bus memory based on FPGA
基于FPGA的一种存储器字节访问方法

It is a widely accepted approach to use wide data bus to increase the data accessing speed. However, this method causes the inconvenience on reading and writing data in bytes. The common operation mechanism of current mainstream SDRAM memory chip was analyzed, and a new byte alignment method was proposed for the SDRAM controller. Based on the given byte-address and input data, the new method could generate correct address and byte control signals, also aligned the bytes to the corresponding positions. The architecture and processing flow were illustrated in detail, as well as the implementation on Field Programmable Gate Array (FPGA) chips. Compared with other schemes based on memory cache and twice-memory-access, this method costs fewer hardware resources and memory bandwidth.